ASIC uArchitecture & Design Engineer
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Applied R&D (AR) consists of target-oriented research either with the goal of solving a particular problem / answering a specific question or for multi-discipline design, development, and implementation of hardware, software, and systems including maintenance support. Supplies techno-economic consulting to clients. AR work is characterised by its detailed and complex nature in order to systematically combine existing knowledge and practices to further developing and incrementally improving products, operational processes, and customer-specific feature development.
Digital Hardware (DHA) comprises the specification, design, and implementation of digital hardware (baseband hardware) while applying design targets such as low cost, high yield, and high reliability. Digital boards are high density boards with numerous components including high speed connections and high precision reference clocks. DHA requires analogue design knowhow and simulation capabilities.
Come create the technology that helps the world act together Nokia is committed to innovation and technology leadership across mobile, fixed and cloud networks. Your career here will have a positive impact on people's lives and will help us build the capabilities needed for a more productive, sustainable, and inclusive world. We challenge ourselves to create an inclusive way of working where we are open to new ideas, empowered to take risks and fearless to bring our authentic selves to work
What we offer Nokia offers continuous learning opportunities, well-being programs to support you mentally and physically, opportunities to join and get supported by employee resource groups, mentoring programs and highly diverse teams with an inclusive culture where people thrive and are empowered.
Nokia is committed to inclusion and is an equal opportunity employer Nokia has received the following recognitions for its commitment to inclusion & equality:
- One of the World's Most Ethical Companies by Ethisphere
- Gender-Equality Index by Bloomberg
- Workplace Pride Global Benchmark
Additional Information US/Canada Nokia Offers a comprehensive benefits package that includes but is not limited to:
- Corporate Retirement Savings Plan
- Health and dental benefits
- Short-term disability, and long-term disability
- Life insurance, and AD&D - Company paid 2x base pay
- Optional or Supplemental life and AD&D insurance (Employee/Spouse/Child)
- Paid time off for holidays and Vacation
- Employee Stock Purchase Plan
- Tuition Assistance Plan
- Adoption assistance
- Employee Assistance Program/Work Life Resource Program
Nokia Maintains broad annual base salary ranges for its roles in order to account for variations in knowledge, skills, experience and market conditions, and with consideration to internal peer equity.(Check the salary ranges in the job info section for this role)
All North America job posts will post for a minimum of 7 calendar days and up to 180 days or until candidate/s identified.
Key Responsibilities:
- Design, implement, and optimize RTL code for complex ASIC components using Verilog/System Verilog, including processors, memory subsystems, and high-speed interfaces.
- Develop modular and reusable RTL code that meets functional, performance, and power requirements.
- Work closely with architecture, design, and verification teams to understand system-level specifications and translate them into efficient, scalable Verilog code.
- Integrate and optimize pre-existing IP blocks (e.g., CPU cores, memory controllers) into the RTL design, ensuring proper functionality and performance.
- Perform timing analysis and ensure the RTL design meets the required timing constraints for high-performance and low-power operation.
- Use simulation tools (e.g., Verdi, VCS, Questa) to verify RTL functionality and identify and resolve bugs during the development cycle.
- Run synthesis and place-and-route tools to convert RTL code to gate-level designs and ensure that the synthesized design meets the performance, area, and power targets.
- Collaborate with cross-functional teams to address design challenges and optimize RTL code for performance, area, and power.
- Document and communicate design decisions, progress, and results.
Required Qualifications:
- Strong proficiency in Verilog for digital circuit design and RTL coding.
- Experience with simulation tools like Verdi, VCS, or Questa to debug and verify RTL designs.
- Familiarity with timing analysis and ensuring timing closure for complex designs.
- Experience with tools and optimization techniques for area, timing, and power.
Other Preferred Qualifications:
- Experience with IP integration, including integrating third-party or pre-designed IP cores into larger RTL systems.
- Experience with multi-core processor designs, interconnect systems, and complex system-level designs.
- Experience with physical design and an understanding of the constraints that affect layout, power, and performance.
How to Submit an Application:
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